There are general trends in mobile communication such as using cellular phones or the like to handle high-frequency signal of several-hundred-MHz, and this raises needs for semiconductor devices having desirable high-frequency characteristics. For example, semiconductor devices such as CMOS-IC and high-voltage-resistance IC use so-called SOI wafer configured so that a silicon oxide film insulating layer is formed on a silicon single crystal substrate (also referred to as base wafer, hereinafter), and further thereon another silicon single crystal layer is formed by stacking as an SOI (Silicon on Insulator) layer. For the case where this is used for semiconductor devices for high-frequency use, it is necessary to use a high-resistivity silicon single crystal as the base wafer in order to reduce high-frequency loss.
One representative method of fabricating the SOI wafer is known as a bonding method. In the bonding method, a first substrate which serves as the base wafer, and a second substrate which serves as an SOI layer in which devices will be formed (also referred to as bond wafer, hereinafter) are bonded while placing a silicon oxide film in between, and the bond wafer is then thinned to a predetermined thickness to as thin as a film, to thereby make the bond wafer into the SOI layer.
The following methods are publicly known as those for thinning the bond wafer.
{circle around (1)} A method in which hydrogen ion is implanted to the bonding surface (referred to as first main surface) of the bond wafer so that a high-hydrogen-concentration layer is formed at a predetermined depth, the bond wafer is bonded to the base wafer, and the bond wafer is then delaminated at the high-hydrogen-concentration layer (so-called Smart Cut (registered trademark)Process).
{circle around (2)} A porous silicon layer is formed by anodization treatment on the bonding surface side of the bond wafer, and a silicon epitaxial layer is formed by vapor-phase epitaxy on the porous silicon layer. The bond wafer is then bonded to the base wafer on its silicon-epitaxial-layer side, and the bond wafer is removed by grinding from the side opposite to the bonding surface to a depth short of the porous silicon layer, or by delamination by jetting a liquid to the porous layer, the residual porous silicon layer is then selectively etched to thereby leave the silicon epitaxial layer as the SOI layer (so-called ELTRAN (registered trademark) Process).
{circle around (3)} A silicon epitaxial layer heavily doped with boron is grown by vapor-phase epitaxy on the bonding surface (referred to as first main surface) side of the bond wafer. The bond wafer is then bonded to the base wafer on its silicon-epitaxial-layer side, and the bond wafer is removed by grinding halfway from the side opposite to the bonding surface. Lastly, the residual portion of the bond wafer is selectively etched based on difference in the boron concentration up to a level of the high-boron-concentration silicon epitaxial layer, to thereby leave the silicon epitaxial layer as the SOI layer (so-called boron etch stop process).
The aforementioned methods, however, suffers from drawbacks as described below. In Smart Cur Process {circle around (1)}, as shown in FIG. 12A, an SOI wafer 50′ (reference numeral 1 denotes a base wafer, and 3 denotes a silicon oxide film) obtained after the delamination has an SOI layer 7′ of which surface having a damaged layer 8 ascribable to the ion implantation, so that roughness of the delamination plane per se is larger than that of mirror-finished surface of a Si wafer or an ordinary product grade. Conventionally, the damaged layer 8 has been mirror-finished by subjecting the surface of the delaminated SOI layer 7′ to mirror polishing having a small polishing depth (generally referred to as touch polishing, where mechano-chemical polishing is adopted). This process results in, as shown in FIG. 12B, a distribution of the film thickness t of the obtained SOI layer of 1.5 to 2 nm or around, in terms of intra-wafer standard deviation σ1. It is also found that, as shown in FIG. 12C, wafers in a wafer lot having the same specification have a distribution of the film thickness t (t1, t2, t3) of approximately 3 nm or larger in terms of inter-wafer standard deviation σ2.
These variations in the film thickness are inevitable in view of technical level of mirror polishing at present, and of no serious problem so far as the thickness of the SOI layer remains at approximately 100 nm or above. There are, however, accelerating trends in micronization and higher integration of CMOS-LSI or the like, which is a major application field of the SOI wafer, so that even a film of 100 nm thick or around, which had been noted as a ultra-thin film up to several years ago, is now no more surprising so much. At present, average film thickness required for ultra-thin-film SOI layer is far thinner than 100 nm, which is reduced to several ten nanometers (20 to 50 nm, for example), and even reduced in some cases to as small as 10 nm or around. In this case, the above-described level of non-uniformity in the film thickness accounts for as much as 10 to several ten percents of the target average film thickness, so that it is a matter of course that this directly results in quality variation of semiconductor devices using the SOI wafer, and lowering in the production yield.
Next, in the ELTRAN process {circle around (2)}, the finally obtained SOI layer is thinned by etch back of the porous Si layer, where a problem resides in that the SOI layer contains, in the surficial portion thereof, a high density of crystal defect such as stacking fault produced in the process of forming an epitaxial layer on the porous Si layer. It is obvious in this case that any trial of touch polishing for removing the crystal defects in the surficial portion will result in the same problem with that in the Smart Cut Process {circle around (1)}.
It is inevitable in the boron etch stop process {circle around (3)}, as shown in FIG. 13A, to adopt process steps in which an epitaxial layer 11 heavily doped with boron is formed on the bond wafer 2, bonding annealing is carried out so as to bond the silicon oxide film 3 to the base wafer 1, and the bond wafer 2 is then thinned by grinding and etch back. Because the bonding annealing is generally carried out at a temperature of as high as 1,000 to 1,300° C., as shown in FIG. 13B, the boron concentration profile in the vicinity of the interface of the epitaxial layer 11 is broadened and loses its sharpness, and this makes etch stop per se impossible. This inevitably requires lowering of the bonding annealing temperature to as low as 800 to 900° C., where another problem arises in that it is made impossible to attain a sufficiently large bonding strength, and that a lot of unbonded areas, called voids, are generated, and that the bond interface becomes more likely to be eroded in the etch back process.
It is therefore a subject of this invention to provide a method of fabricating an SOI wafer, which can suppress both of the intra-wafer uniformity of the firm thickness and the inter-wafer uniformity of the film thickness to an enough small level even when a required level for the thickness of the SOI layer is extremely small, and can suppress the quality variation and raise the production yield even when the SOI wafer is processed to obtain ultra-fine, highly integrated CMOS-LSI or the like.